The present invention generally relates to forming contacts and vias with improved overlap to small underlying conductors. In particular, the present invention relates to forming contacts and vias on a sub-lithographic scale using chemical vapor deposition and etch back processing.
In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these high densities there has been and continues to be efforts toward scaling down the device dimensions on semiconductor wafers. In order to accomplish such high device packing density, smaller and smaller features sizes are required as well as increased multilevel architecture. This includes the width and spacing of interlevel connections, such as contacts and vias. Since numerous contacts and vias are typically present on a semiconductor wafer, the trend toward higher device densities is a notable concern.
An interlevel connection typically includes a landing conductor, directly over which a contact is formed. Generally speaking, lithographic process limitations determine the minimum conductor width required for landing an interlevel connection. An underlying conductor must possess a width large enough to accommodate the via (the diameter of the via) in addition to providing some margin for misalignment between the respective layers. As the trend toward higher device densities continues, it is increasingly difficult to form vias/contacts directly over landing conductors. FIGS. 1 and 2 illustrate common problems associated with forming vias/contacts over and underlying conductor.
Referring to FIG. 1, an incomplete landing is illustrated. The via 10 is too wide over underlying conductor 12 within the insulating material 14. The incomplete landing is primarily due to the limitations of printing dimension. Referring to FIG. 2, another incomplete landing is illustrated. The via 10 is not directly positioned over underlying conductor 12 within the insulating material 14. The incomplete landing is primarily due to misalignment of the respective layers. The problems illustrated in FIGS. 1 and 2 can lead to shorting out, contamination, and other deleterious effects to the conductor and/or insulator materials. And these problems are exacerbated by the trend to decrease the width of features such as the underlying conductor, especially at dimensions of about 0.25 xcexcm or less.
Patterning features having dimensions of about 0.25 xcexcm or less with acceptable resolution is difficult at best, and impossible in some circumstances. Patterning interlevel connections including contacts and vias with small dimensions is required in order to participate in the continuing trend toward higher device densities. Procedures that increase resolution, improved critical dimension control, and provide small features are therefore desired. Particularly, procedures that permit complete landing of interlevel connections over underlying conductor are desired.
The present invention provides methods of forming sub-lithographic features. The present invention more particularly provides sub-lithographic features that are particularly useful for forming interlevel connections. Using the methods of the present invention, it is possible to form fully landed contacts and vias over underlying conductors, despite the small size of the underlying conductors. As a result, the present invention effectively addresses the concerns raised by the trend towards the miniaturization of semiconductor devices.
In one embodiment, the present invention relates to a method of forming a sub-lithographic via, involving the steps of providing a substrate comprising a conductor having a width of about 0.25 xcexcm or less over a portion of the substrate and an insulating film over the conductor and the substrate; etching a preliminary via in the insulating film over the conductor, the preliminary via defined by sidewalls in the insulating film; depositing a CVD layer over the substrate, the insulating film, and the conductor, the CVD layer having a vertical portion adjacent the sidewalls of the insulating film and a horizontal portion in areas not adjacent the sidewalls of the insulating film; and removing the horizontal portion of the CVD layer thereby forming the sub-lithographic via over the conductor, the sub-lithographic via having a width of less than about 0.25 xcexcm.
In another embodiment, the present invention relates to a method of forming a sub-lithographic contact, involving the steps of providing a substrate comprising a conductor having a width of about 0.25 xcexcm or less over a portion of the substrate and an insulating film over the conductor and the substrate; etching a preliminary via in the insulating film over the conductor, the preliminary via defined by sidewalls in the insulating film; depositing a CVD layer over the substrate, the insulating film, and the conductor, the CVD layer having a vertical portion adjacent the sidewalls of the insulating film and a horizontal portion in areas not adjacent the sidewalls of the insulating film; removing the horizontal portion of the CVD layer thereby forming the sub-lithographic via over the conductor, the sub-lithographic via having a width of less than about 0.25 xcexcm; and depositing a conductive material into the sub-lithographic via thereby forming the sub-lithographic contact.
In yet another embodiment, the present invention relates to a method of forming a sub-lithographic interlevel contact, involving the steps of providing a substrate comprising a conductor having a width of about 0.25 xcexcm or less over a portion of the substrate and an insulating film over the conductor and the substrate, the conductor comprising at least one of aluminum, copper, titanium, and tungsten; etching a preliminary via in the insulating film over the conductor, the preliminary via defined by sidewalls in the insulating film; depositing a CVD layer over the substrate, the insulating film, and the conductor, the CVD layer having a vertical portion adjacent the sidewalls of the insulating film and a horizontal portion in areas not adjacent the sidewalls of the insulating film, the CVD layer having a thickness from about 100 xc3x85 to about 3,000 xc3x85; removing the horizontal portion of the CVD layer thereby forming the sub-lithographic via over the conductor, the sub-lithographic via having a width of less than about 0.25 xcexcm; and depositing a conductive material into the sub-lithographic via thereby forming the sub-lithographic contact, the conductive material comprising at least one of aluminum, copper, titanium, and tungsten.